1. Field of the Invention
The present invention relates generally to flip-flops and relates more particularly to flip-flops with scan capabilities.
2. Background Art
The design of a computer system may be broken down into three parts—system design, logic design, and circuit design. System design involves breaking the overall system into subsystems and specifying the characteristics of each subsystem. For example, system design of a computer system could involve specifying the number and type of memory units, arithmetic units, and input-output devices as well as the interconnection and control of these subsystems. Logic design involves determining how to interconnect basic logic building blocks to perform a specific function. An example of logic design is determining the interconnection of logic gates and flip-flops to perform binary addition. Circuit design involves specifying the interconnection of specific components such as resistors, diodes, and transistors to form logic building blocks.
Two such logic building blocks are latches and flip-flops. A latch is a memory element that provides storage for at least one bit, i.e., it can at least store a ‘1’ or a ‘0.’ FIG. 1 shows a typical embodiment of a latch. The latch (10) shown in FIG. 1 has two NOR gates, NOR_1 (12) and NOR_2 (14), which are positioned in a symmetrical configuration. A first input to the latch (10), IN_1, serves as an input to NOR_1 (12), and a second input to the latch (10), IN_2, serves as an input to NOR_2 (14). The output of NOR_1 (12) is connected to both an output of the latch (10), OUT, and to a second input of NOR_2 (14). The output of NOR_2 (14) is connected to both a second output of the latch (10), OUT0, and to a second input of NOR_1 (12).
When IN_1 goes high, i.e., ‘1,’ OUT0 is “reset” to low, i.e., ‘0.’ Alternatively, when IN_2 goes high, OUT0 is “set” to high. When both IN_1 and IN_2 go low, the value of OUT0 goes to the value of OUT before IN_1 and IN_2 went low. Further, IN_1 and IN_2 are typically not allowed to go high at the same time, since doing so causes the latch (10) to become unstable. The behavior of the latch (10) shown in FIG. 1 (also known as a “Set-Reset latch”) is summarized by the next state transition table given in Table 1.
TABLE 1Next state transition table for latch referenced in FIG. 1IN_1IN_2OUTOUT0000000110101011110001010110—111—
Moreover, embodiments of latches that are not symmetrical, unlike the one depicted in FIG. 1, are called skewed latches.
Flip-flops, like latches, are memory elements that provide storage for at least one bit, i.e., it can at least store a ‘1’ or a ‘0.’ However, a flip-flop differs from a latch in that the output of the flip-flop is not only dependent on the present input, but also dependent on the past sequence of inputs. Additionally, a flip-flop differs from a latch in that a flip-flop is triggered by rising and/or falling edges of an input signal whereas a latch operates is level sensitive, i.e., operates on a high phase and/or low phase of an input signal.
FIG. 2 shows a typical embodiment of a flip-flop. The flip-flop (20) has two AND gates, AND_1 (22) and AND_2 (24), and two NOR gates, NOR_1 (26) and NOR_2 (28). A first input to the flip-flop (20), IN_1, serves as an input to AND_1 (22), and a second input to the flip-flop (20), IN_2, serves as an input to AND_2 (24). A clock input, CLK, also serves as an input to both AND_1 (22) and AND_2 (24). The output from AND_1 (22) serves as an input to NOR_1 (26), and the output from AND_2 (24) serves as an input to NOR_2 (28). The output from NOR_1 (26) is connected to an output of the flip-flop (20), OUT, a second input to NOR_2 (28), and to a third input to AND_1 (22). The output from NOR_2 (28) is connected to a second output of the flip-flop (20), OUT0, a second input to NOR_1 (26), and to a third input to AND_2 (24).
The flip-flop (20) shown in FIG. 2 is designed such that it changes state a short time (ε) after the falling edge of CLK provided that IN_1 and IN_2 have appropriate values. For example, if IN_1, IN_2, and OUT0 are low in the present state before a CLK pulse, then after the CLK pulse, AND_1 (22) outputs low to an input of NOR_1 (26) and AND_2 (24) outputs low to an input of NOR_2 (28). Since OUT0 was low before the clock pulse, a low was inputted to an input of NOR_1 (26), which, in turn, causes NOR_1 (26) to output high since both inputs to NOR_1 (26) are low. The high output from NOR_1 (26) goes to the second input of NOR_2 (28), which then causes NOR_2 (28) to output low to OUT0 since one input to NOR_2 (28) is high and another input to NOR_2 (28) is low. In summary, when IN_1, IN_2, and OUT0 are low in the present state, then in the next state, OUT0 remains low.
The same procedure described above can be applied to any combination of present state inputs to determine the next state output. Note that the value of OUT0 in the present state becomes the value of OUT in the next state. The behavior of the flip-flop (20) described in FIG. 2 (also known as a “clocked J-K flip-flop”) is summarized by the next state transition table shown in Table 2.
TABLE 2Next state transition table for flip-flop referenced in FIG. 2IN_1IN_2OUTOUT000001000010111010011101001111110
An important aspect of circuit design is how logic building blocks, such as latches and flip-flops, are actually implemented in a computer system. A typical approach used to implement logic building blocks is through the use of complementary metal-oxide-semiconductor (“CMOS”) logic families.
CMOS logic families use metal-oxide-semiconductor field-effect (“MOSFET”) transistors. The use of MOSFET transistors is beneficial because almost no current is needed to operate the transistors. However, MOSFETs operate slower than devices used in other logic families. MOSFETs may be divided into two types of transistors: positive-channel metal-oxide semiconductor (“PMOS”) transistors and negative-channel metal-oxide semiconductor (“NMOS”) transistors. A transistor is ‘on’ when there is an electrical pathway across the transistor such that a voltage at one terminal of the transistor can be seen at another terminal of the transistor. NMOS transistors can be switched ‘on’ or ‘off’ by the movement of electrons, whereas PMOS transistors can be switched ‘on’ or ‘off’ by the movement of electron vacancies. A MOSFET has a voltage threshold (“VT”) value, which is the voltage level at which the MOSFET switches ‘on’ or ‘off.’ Generally, a NMOS transistor switches ‘on’ when there is a high voltage applied to the input of the NMOS transistor and a PMOS transistor switches ‘on’ when there is a low voltage, e.g., ground, applied to the input of the PMOS transistor.
An implementation where the use of MOSFETs is exemplified involves a master-slave flip-flop, a type of flip-flop that is well known to those of ordinary skill in the art. FIG. 3 shows a typical embodiment of a master-slave flip-flop (30). The master-slave flip-flop (30) includes a master stage (32) that drives a slave stage (34).
The master stage (32) employs a first PMOS transistor (36), a first NMOS transistor (38), a first inverter (40), and a second inverter (42). The first PMOS transistor (36) and the first NMOS transistor (38) are in parallel (also referred to as “master transmission gate”), meaning that a terminal of the first PMOS transistor (36) is connected to a terminal of the first NMOS transistor (38) (also referred to as “first joint terminal”) and a second terminal of the first PMOS transistor (36) is connected to a second terminal of the first NMOS transistor (38) (also referred to as “second joint terminal”).
A data input, DATA, serves as an input to the master stage (32). DATA is connected to the first joint terminal of the first PMOS transistor (36) and the first NMOS transistor (38). An external clock signal, CLK, serves as an input to the first PMOS transistor (36). An external complement of CLK, CLK′, serves as an input to the first NMOS transistor (38). The second joint terminal of the first PMOS transistor (36) and the first NMOS transistor (38) is connected to an input to the first inverter (40). The first inverter (40) outputs to both an input of the second inverter (42) and to the slave stage (34) of the master-slave flip-flop (30). The second inverter (42) outputs to the input of the first inverter (40).
The slave stage (34) employs a second PMOS transistor (44), a second NMOS transistor (46), a third inverter (48), and a fourth inverter (50). The second PMOS transistor (44) and the second NMOS transistor (46) are in parallel (also referred to as “slave transmission gate”), meaning that a terminal of the second PMOS transistor (44) is connected to a terminal of the second NMOS transistor (46) (also referred to as “third joint terminal”) and a second terminal of the second PMOS transistor (44) is connected to a second terminal of the second NMOS transistor (46) (also referred to as “fourth joint terminal”).
As discussed above, the output from the first inverter (40) in the master stage (32) serves as an input to the slave stage (34). The output from the first inverter (40) in the master stage (32) is connected to the third joint terminal of the second PMOS transistor (44) and the second NMOS transistor (46). The external complement of CLK, CLK′, serves as an input to the second PMOS transistor (44). The clock signal, CLK, serves as an input to the second NMOS transistor (46). The fourth joint terminal of the second PMOS transistor (44) and the second NMOS transistor (46) is connected to an input to the third inverter (48). The third inverter (48) outputs to both an input to the fourth inverter (50) and to an output of the master-slave flip-flop (30), OUT. The fourth inverter (50) outputs to the input of the third inverter (48).
When CLK goes low, the first PMOS transistor (36) switches ‘on.’ Since CLK goes low, CLK′ accordingly goes high, and the first NMOS transistor (38) switches ‘on.’ Because both the first PMOS transistor (36) and the first NMOS transistor (38) switch ‘on,’ the master transmission gate is conducting, i.e., the master transmission gate is ‘on,’ and DATA passes through the master transmission gate to the input of the first inverter (40). The first inverter (40) then outputs an inverted DATA value to both the input of the second inverter (42) and to the input of the slave stage (34). The second inverter (42) outputs a buffered, non-inverted value of DATA back to the input of the first inverter (40). The main function of the second inverter (42) is to ensure that the first inverter (40) holds its output even if the conduction of DATA through the master transmission gate attenuates.
Since CLK goes low and CLK′ follows high, the second NMOS transistor (46) and the second PMOS transistor (44) switch ‘off,’ respectively. Because both the second PMOS transistor (44) and the second NMOS transistor (46) switch ‘off,’ the slave transmission gate does not conduct, i.e., the slave transmission gate is ‘off,’ and the input to the slave stage (34) from the output of the first inverter (40) in the master stage (32) does not pass through the slave transmission gate to the input of the third inverter (48).
Alternatively, when CLK goes high and CLK′ follows low, the first PMOS transistor (36) and the first NMOS transistor (38) switch ‘off,’ respectively. Accordingly, this causes the master transmission gate to switch ‘off’ so that DATA does not pass through the master transmission gate to the input of the first inverter (40). However, recall that, due to the function of the second inverter (42), the first inverter (40) continues to output the value that was being outputted by it when the master transmission gate was switched ‘on.’
Since CLK goes high and CLK′ follows low, the second PMOS transistor (44) and the second NMOS transistor (46) switch ‘on,’ respectively. Accordingly, this causes the slave transmission gate to switch ‘on’ so that the output from the first inverter (40) passes through the slave transmission gate to the input of the third inverter (48). The third inverter (48) then outputs an inverted value of the input to the slave stage (34) from the first inverter (40) to both the input of the fourth inverter (50) and to OUT. The fourth inverter (50) outputs a buffered, non-inverted value of the input to the slave stage (34) back to the input of the third inverter (48). The main function of the fourth inverter (50) is to ensure that the third inverter (42) holds its output even if the conduction of the input to the slave stage (34) through the master transmission gate attenuates.
In summary, in the master-slave flip-flop (30) shown in FIG. 3, data is passed from the input of the master-slave flip-flop (30) to the output of the master-slave flip-flop (30) sequentially through a master stage (32) and a slave stage (34). When the master stage (32) is active, data is passed through the master stage (32) to the slave stage (34), and when the slave stage (34) is active, data is passed from the output of the master stage (32) to the output of the master-slave flip-flop (30). Further, the master stage (32) and slave stage (34) are typically not either both active or inactive at the same time.
An additional feature of a master-slave flip-flop, and other types of flip-flops, involves including scan capabilities in addition to conventional flip-flop functions. Scan circuitry is added to a flip-flop on top of the flip-flop circuitry to allow data within a flip-flop to be scanned or scan data to be inputted into the flip-flop to test the functionality of the flip-flop. Flip-flops with scan circuitry are often used in high performance systems such as high-speed microprocessors.
FIG. 4 shows a typical embodiment of a flip-flop with scan capabilities. The flip-flop with scan capabilities (60) shown in FIG. 4 includes a first stage (62) and a second stage (74).
The first stage (62) employs a first PMOS transistor (64), a first NMOS transistor (66), a second PMOS transistor (68), a second NMOS transistor (70), and a latch block (72). The first PMOS transistor (64) and the first NMOS transistor (66) are in parallel (also referred to as “data transmission gate”), meaning that a terminal of the first PMOS transistor (64) is connected to a terminal of the first NMOS transistor (66) (also referred to as “first joint terminal”) and a second terminal of the first PMOS transistor (64) is connected to a second terminal of the first NMOS transistor (66) (also referred to as “second joint terminal”). The second PMOS transistor (68) and the second NMOS transistor (70) are also in parallel (also referred to as “scan transmission gate”), meaning that a terminal of the second PMOS transistor (68) is connected to a terminal of the second NMOS transistor (70) (also referred to as “third joint terminal”) and a second terminal of the second PMOS transistor (68) is connected to a second terminal of the second NMOS transistor (70) (also referred to as “fourth joint terminal”). The second joint terminal of the first PMOS transistor (64) and the first NMOS transistor (66) is connected to an input of the latch block (72). Likewise, the fourth joint terminal of the second PMOS transistor (68) and the second NMOS transistor (70) is connected to the input of the latch block (72). The latch block (72) functions as a latch (described above in reference to FIG. 1), and outputs to the second stage (74), which functions similarly to a slave stage (described above in reference to FIG. 3).
A clock signal, CLK, serves as an input to the first stage (62). CLK is connected to an input of the first PMOS transistor (64). A data input, DATA, also serves as an input to the first stage (62). DATA is connected to the first joint terminal of the first PMOS transistor (64) and the first NMOS transistor (66). Additionally, a complement of CLK, CLK′, serves as an input to the first stage (62). CLK′ is connected to an input of the first NMOS transistor (66).
A scan clock signal, SCLK, serves as an input to the first stage (62). SCLK is connected to an input of the second PMOS transistor (68). A scan input, SI, also serves as an input to the first stage (62). SI is connected to the third joint terminal of the second PMOS transistor (68) and the second NMOS transistor (70). Additionally, a complement of SI, SI′, serves as an input to the first stage (62). SI′ is connected to an input of the second NMOS transistor (70).
During normal mode operation of the flip-flop with scan capabilities (60), CLK is enabled and SCLK is disabled. Accordingly, as CLK pulses (causing CLK′ to also pulse), the data transmission gate continuously switches ‘on’ and ‘off’ at the rate at which CLK pulses. This allows DATA to pass through the data transmission gate to the input of the latch block (72) during the cycles when the data transmission gate is switched ‘on.’
Alternatively, during scan mode operations, SCLK is enabled and CLK is disabled. Accordingly, as SCLK pulses (causing SCLK′ to also pulse), the scan transmission gate continuously switches ‘on’ and ‘off’ at the rate at which SCLK pulses. This allows SI to pass through the scan transmission gate to the input of the latch block (72) during the cycles when the scan transmission gate is switched ‘on.’